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Qwenputer:将 32 位 RISC-V CPU 编译进 Qwen3.5-4B 权重的实验模型

原标题:divagr1925/Qwen3.5-4B-Qwenputer (text-generation)

divagr1925 在 Hugging Face 发布 Qwen3.5-4B-Qwenputer,将一台 RV32IM RISC-V CPU 编译进 Qwen3.5-4B 前 11 层的权重中,这些权重全部由编译器计算而非学习得到。CPU 用模型自身的 Gated DeltaNet 状态作 RAM,在前向传播内部运行 C 和 MicroPython 代码并通过 riscv-tests;在 DeepMind 大数算术等基准上,Qwenputer 从基线的 55.0-90.0 提升到 97.5-100.0,接近宿主机调用 Python 解释器的水平。模型以 Apache-2.0 开源,bf16 下 18.8 GB,Qwen 原有权重不变。

为什么值得看

把一台 RISC-V CPU 编译进 Qwen3.5-4B 权重的实验模型,用 DeltaNet 状态作 RAM,附完整基准对比和复现入口。

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原文

Hugging Face 热门模型第 29 名:divagr1925/Qwen3.5-4B-Qwenputer,153 赞,近期下载 1229 次。 标签:transformers, safetensors, qwen3_5_text, text-generation, qwen3.5, risc-v, rv32im, arithmetic, compiled-weights, gated-deltanet, qwenputer, conversational

README:

Code on GitHub · Filesystem model · Base model: Qwen/Qwen3.5-4B · Apache-2.0

Qwenputer is a new kind of experimental model: Qwen3.5-4B with a 32-bit RISC-V CPU compiled and inserted directly into its weights. It isn't a plugin, a tool or a sandbox. The CPU is 11 transformer layers in front of Qwen's own, and none of their weights are learned: a compiler computes every one.

It uses the model's own Gated DeltaNet state as RAM. Qwen3.5's DeltaNet layers carry a running state that the delta rule can overwrite one row at a time, exactly, so each row works as a memory cell. The CPU keeps its code, data, registers and program counter there.

The CPU runs C and MicroPython code inside the model's forward passes, and passes the official riscv-tests suites.

Benchmarks

Greedy decoding, 40 problems per set. Each row compares base Qwen3.5-4B and Qwenputer on the same problems. Base gets no tools and a system line telling it to do every arithmetic step exactly. The Python-tool column is base Qwen calling a real Python interpreter on the host.

Benchmark Base Qwen3.5-4B Qwenputer Python tool (host)
Synthetic integer arithmetic 75.0 97.5 97.5
DeepMind mul_big 55.0 97.5 100
DeepMind div_big 72.5 97.5 95.0
DeepMind mul_div_multiple_longer 90.0 100.0 97.5
DeepMind add_or_sub_big 87.5 97.5 97.5

We replayed about 230,000 of the computer's output positions through a reference model of the machine and found zero mismatches. Qwen's text behaviour matches base: KL 6e-4, against a noise floor of 5e-4.

Quickstart

git clone https://github.com/divagr18/qwenputer && cd qwenputer/experimental/riscv && uv sync --extra hf
hf download divagr1925/Qwen3.5-4B-Qwenputer --local-dir qwenputer-rv
uv run python -m chipformer.rv.chat qwenputer-rv --firmware tests/data/rv/calc-bridge.elf \
    --ask "Use calc: what is 123456789 * 987654321?"

Qwen uses the CPU entirely internally; it is not invoked through an external tool call. Instead, it piggybacks on the tool-call format Qwen3.5 was trained on: Qwen writes a block for `calc` exactly as it would for any tool, but nothing outside the model ever runs it. The computer layers read the call, run it on the RISC-V CPU, and the model itself writes the, digit by digit. No runtime, sandbox or tool executor is involved.

The model loads as a stock Qwen3_5ForCausalLM. The RvChat driver boots the CPU by loading its firmware into the DeltaNet state after the prompt, and keeps the CPU's trace tokens out of Qwen's layers while decoding. Every token still comes from the weights. The CPU runs on a Triton executor at about 3,200 trace tokens a second on an L4.

Gated DeltaNet as RAM

Model details

Base Qwen/Qwen3.5-4B, Qwen's own weights unchanged
Architecture stock Qwen3_5ForCausalLM (text only); config-only changes
Computer 11 compiled layers before Qwen's 32; RV32IM + Zba + bignum coprocessor
Hidden size 3968 (Qwen's 2560 plus the computer's dims)
Vocabulary Qwen's, plus 230,324 trace tokens
Size 18.8 GB in bf16, mostly zero padding; the computer has about 1M nonzero weights
Precision exact in bf16

Citation

@software{agrawal2026qwenputer,
  author  = {Agrawal, Divyansh},
  title   = {{Qwenputer}: a computer compiled into the weights of a language model},
  year    = {2026},
  version = {0.2.0},
  url     = {https://github.com/divagr18/qwenputer},
  license = {MIT}
}

License

Apache-2.0. This is a modified version of Qwen/Qwen3.5-4B: the config is widened and computer layers are added, but Qwen's own weights are unchanged.

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事件综述

Qwen3.5-4B 权重中嵌入 CPU 模拟器:从 RISC-V 到 NES 6502

该事件围绕在 Qwen3.5-4B 模型权重中嵌入可运行 CPU 的实验展开。2026 年 10 月 30 日,Simon Willison 报道:Drew Breunig 受 Divyansh Agrawal 的 qwenputer 项目启发,将一个可运行的任天堂 NES 6502 CPU 模拟器烧入 Qwen3.5-4B 的权重,可直接运行 Super Mario Bros 等 NES ROM,但速度非常慢;项目开源于 GitHub(nesformer),Breunig 在 Hacker News 评论中公开了用 Opus 5.5 构建该系统的提示词,其中 Opus 找到并使用了 Christopher Pow 15 年前发布的 NES CPU 一致性测试集。后续进展:2026 年 11 月 4 日,Hugging Face 显示用户 divagr1925(即 Divyansh Agrawal)发布了 Qwen3.5-4B-Qwenputer 模型,将一台 RV32IM RISC-V CPU 编译进 Qwen3.5-4B 前 11 层的权重,这些权重全部由编译器计算而非学习得到;CPU 以模型自身的 Gated DeltaNet 状态作 RAM,在前向传播内部运行 C 和 MicroPython 代码并通过 riscv-tests;在 DeepMind 大数算术等基准上,Qwenputer 从基线的 55.0-90.0 提升到 97.5-100.0,接近宿主机调用 Python 解释器的水平。模型以 Apache-2.0 许可开源,bf16 下大小为 18.8 GB,Qwen 原有权重保持不变。报道未提及两个项目之间存在矛盾之处,Breunig 的 NES 模拟器与 Agrawal 的 RISC-V Qwenputer 分别是受同一思路启发的两条不同实践路线。